Non-volatile memory devices and systems including multi-level cells using modified read voltages and methods of operating the same

ABSTRACT

Methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, which is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device. Related devices and systems are also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from Korean Patent Application No. 10-2007-0064543, filed in the Korean Intellectual Property Office on Jun. 28, 2007, the disclosure of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to the field of electronics, and more particularly, to multi-level cells in non-volatile memories and the methods of operating multi-level cells in non-volatile memories.

BACKGROUND

EEPROM cells that support multiple programmed states are typically referred to as multi-level cells (MLC). As illustrated by FIG. 1, an MLC that supports an erased state and three different programmed states operates to store two data bits per cell. These and other aspects of an MLC having two data bits per cell is disclosed in an article by Takeuchi et al., entitled “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp. 1228-1238, August (1998). Commonly assigned U.S. Pat. Nos. 5,862,074 and 5,768,188 also disclose aspects of multi-level EEPROM cells arranged in a NAND-type configuration, the disclosures of which are hereby incorporated herein by reference.

As further shown in FIG. 1, the different states supported by the MLC can be read using different threshold voltages as shown. For example, applying a threshold voltage between V₁ and V₂ will ideally activate the MLC if the cell is programmed to state 1. Furthermore, the other states can be discriminated from the first state using the different threshold voltages shown.

As shown in FIG. 2, one of the issues that can arise in using an MLC is that as the MLC is used to store more bits of information (such as a four bit MLC) the margin which may otherwise be present between the different states can be reduced so that less margin is available for the threshold voltage used to discriminate between the different states. Furthermore, several external factors (such as coupling and leakage, etc.) can further increase the distribution of the threshold voltages for the states. As shown in FIG. 2, the distribution of the threshold voltage that will activate cells in different states can overlap as shown by the highlighted regions. This overlap in threshold voltages for the different states can cause the MLC to generate errors when being read.

SUMMARY

Embodiments according to the invention can provide non-volatile memory devices and systems including multi-level cells using modified read voltages and methods of operating the same. Pursuant to these embodiments, methods of operating a multi-level non-volatile memory device can include accessing data, stored in the device, that is associated with read voltages and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device.

In some embodiments according to the invention, a method of operating a multi-level non-volatile memory device can include receiving a read operation to read data from a plurality of multi-level non-volatile memory cells associated with a word line. A range of preliminary read voltages are applied to the word line between an upper read voltage limit for a first state and a lower read voltage limit for a second state that is immediately adjacent to the first state. A determination is made as to which of the preliminary read voltages activated a minimum number of the plurality of multi-level non-volatile memory cells to provide a read voltage to discriminate between the first and second states. The read voltage is applied to the word line to read the plurality of multi-level non-volatile memory cells to execute the read operation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of threshold voltage distributions for multi level cells (MLC) for a two bit MLC supporting four different states.

FIG. 2 is a schematic illustration of threshold voltage distributions for MLCs capable of storing eight states where coupling, leakage, etc. can result in overlapping threshold voltages for different states.

FIG. 3 is a block diagram that illustrates an array of MLCs accessed using a read voltage modified by a read voltage adjustment circuit and provided to a high voltage generator circuit in some embodiments according to the invention.

FIG. 4 is a schematic representation of a plurality of adjacent states stored by an MLC having overlapping distributions of threshold voltages and selected modified read voltages used to discriminate between the adjacent states in some embodiments according to the invention.

FIG. 5 is a schematic representation of a distribution of threshold voltages for two adjacent states in an MLC affected by high density programming of data bits in the MLC and a range of preliminary voltages applied to the MLC for determining a modified read voltage used to discriminate between the states in some embodiments according to the invention.

FIG. 6 is a flowchart that illustrates operations of a read voltage adjustment circuit used to determine a modified read voltage by applying the range of preliminary voltages to the MLCs to reduce the likelihood of an error due to the overlapping distribution of threshold voltages in some embodiments according to the invention.

FIGS. 7 and 8 are flowcharts that illustrate operations of a read voltage adjustment circuit to determine a number of MLCs which are activated in response to an applied preliminary voltage within the preliminary voltage range in some embodiments according to the invention.

FIG. 9 is a schematic representation of distributions of threshold voltages used to access MLCs storing data representing different states in a four bit MLC non-volatile memory where the data is organized as four logical pages in some embodiments according to the invention.

FIG. 10 is a flowchart that illustrates operations of a read voltage adjustment circuit used to determine read voltages applied by a high voltage generator circuit on a per state and per page basis in some embodiments according to the invention.

DESCRIPTION OF EMBODIMENTS ACCORDING TO THE INVENTION

The present invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown by way of example. The present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

It will be understood that when an element is referred to as being “connected to,” “coupled to” or “responsive to” (and/or variants thereof) another element, it can be directly connected, coupled or responsive to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected to,” “directly coupled to” or “directly responsive to” (and/or variants thereof) another element, there are no intervening elements present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising” (and/or variants thereof), when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” (and/or variants thereof) when used in this specification, specifies the stated number of features, integers, steps, operations, elements, and/or components, and precludes additional features, integers, steps, operations, elements, and/or components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As described herein in greater detail, embodiments according to the present invention can provide non-volatile memory devices including multi level cells (MLC) that are accessed using read voltages that are modified based on the application of incremental read voltages to determine a preferred voltage level used to discriminate between states stored by the MLC. For example, in some embodiments according to the invention, the MLC can be used to store 16 different states (i.e., four bits of data).

As appreciated by the present inventor, when the MLCs are used to store many states, the distribution of threshold voltages for the different states can increase compared to when relatively few states are stored in the MLC. Accordingly, the distributions of the threshold voltages associated with the different states (and particularly the states which are immediately adjacent to one another) can overlap one another so that an MLC that is used to store, for example, a fifth state can be activated in response to a threshold voltage which would otherwise fall within the nominal range of threshold voltages for the fourth state. If left unaddressed, this type of phenomenon can lead to an error during a read operation. Therefore, as appreciated by the present inventor, modifying the read voltages used to access the MLC may reduce the likelihood that an MLC storing an immediately adjacent state is erroneously activated.

In some embodiments according to the invention, the read voltages applied to the MLCs are modified in response to each read operation that is provided to the multilevel non volatile memory device. For example, in some embodiments according to the invention, the non-volatile memory device can determine the read voltage to be used to most likely discriminate between the states before providing the requested data.

In still further embodiments according to the invention, the read voltages used to access the MLCs to discriminate between states can be provided by applying a range of preliminary read voltages to the word lines associated with the cells. The preliminary read voltages can range between an upper read voltage limit for a first state stored by the MLC (i.e., a state associated with a lower threshold) up to a lower read voltage limit for a second state that is immediately adjacent to the first state (i.e., a state having a threshold voltage associated therewith which is immediately greater than the threshold voltage associated with the first state).

During the application of the range of preliminary read voltages, a read voltage adjustment circuit can determine which of these preliminary read voltages activated a minimum number of the MLCs. The read voltage that is associated with activation of the minimum number of MLCs can be used as the read voltage to discriminate between the first and second states. The read voltage adjustment circuit can then store the determined read voltage in a high voltage generator circuit which is used to apply the stored read voltage to the MLC array in response to the read operation.

Furthermore, as briefly described above, the read voltage adjustment circuit can modify the read voltage stored by the high voltage generator circuit during subsequent read operations. Accordingly, modifying the read voltage in response to read operations can provide a continuously tuned read voltage that increases the likelihood that only those cells which store a particular state are activated in response to the read operation.

In still further embodiments according to the invention, the read voltage adjustment circuit can determine the minimum number of MLCs activated within the preliminary voltage range by accessing the MLCs using each of the incremental preliminary read voltages in determining how many of the MCLs produce data which is different from the immediately proceeding read (i.e., how many bits produced by the MLCs have toggled). The number of toggled bits for each of the cycles can then be compared to determine which of the read voltages produced the minimum number of activated MLCs. The read voltage associated with this minimum number of activated MLCs can then be used as the read voltage for that particular state.

In further embodiments according to the invention, the read voltage adjustment circuit can determine the minimum number of activated MLCs by accessing the MLCs using the incremented preliminary read voltages and examining how many of the MLCs are activated for each increment. Again, the read voltage adjustment circuit can then determine which of the incremental voltages activated the fewest MLCs. The preliminary read voltage associated with the minimum activated MLCs can then be used to provide read voltage for subsequent read operations.

FIG. 3 is a schematic illustration of an MLC non-volatile memory device 100 in some embodiments according to the invention. The device 100 includes an MLC array 110 including a plurality of MLCs arranged in rows 111, 112 . . . 113. Each of the rows of the MLCs is coupled to a respective word line that is driven by a row decoder circuit 170 (sometimes referred to as an X decoder circuit).

The row decoder circuit 170 can control activation of the MLCs in each of the rows 111-113 in response to control voltages provided by a high voltage generator circuit 160. In particular, the high voltage generator circuit 160 can provide a verify voltage the V_(verify) a read voltage V_(read) and a program voltage V_(program). The high voltage generator circuit 160 can control the row decoder circuit 170 in response to control signals provided by a command register and control logic circuit 150 that operates responsive to signals provided from outside the device 100.

The MLC array 100 is also coupled to a page buffer circuit 120 that stores data accessed from the rows of MLCs 111-113 in response to the control signals provided by the high voltage generator circuit 160. The data stored by the page buffer circuit 120 is provided to a column gate circuit 130 (sometimes referred to as a Y gate) that operates to provide selected data from the page buffer circuit 120 to a read voltage adjustment circuit 140.

The read voltage adjustment circuit 140 operates to modify the read voltages applied to the MLCs in the array 110 to discriminate between states stored by the MLCs in response to a read operation. In particular, the read voltage adjustment circuit 140 can provide a read voltage to the high voltage generator circuit 160 to modify the read voltage applied by the high voltage generator circuit 160 to the MLCs in the array 110.

Further, the read voltage adjustment circuit 140 can also provide a row address to the row decoder circuit 170 to control which of the rows of MLCs 111-113 is accessed using the read voltage provided by the high voltage generator circuit 160. In turn, when the data accessed using the read voltage is provided by the selected row of MLCs 111-113, the data is provided to the page buffer circuit 120. The buffer circuit 120, in turn, provides data to the column gating circuit 130 which, under the control of a column address from the read voltage adjustment circuit 140, provides selected data. The read voltage adjustment circuit 140 can then examine the data provided by the accessed row of MLCs using a read voltage to determine if the read voltage is one which will reduce the likelihood of errors.

Further, in operation, the read voltage adjustment circuit 140 can repeatedly increment the read voltage provided to the high voltage generator circuit 160 and, in turn, examine the data produced by the accessed row of MLCs to determine if that particular read voltage activated a minimum number of MLCs. Once the read voltage adjustment circuit 140 determines the read voltage that activated a minimum number of MLCs, the corresponding read voltage can be stored in a register 161 in the high voltage generator circuit 160 for use in accessing the MLCs in response to a read operation.

It will be understood that the read voltage stored in the register 161 can be updated periodically by the read voltage adjustment circuit 140 in some embodiments according to the invention. In other embodiments according to the invention, the read voltage adjustment circuit 140 can modify the read voltage used to access the MLCs in response to each read operation provided to the device 100.

FIG. 4 is a schematic illustration of a distribution of threshold voltages corresponding to respective states stored by the MLCs for both an idealized situation as well as situations where the MLCs are affected by leakage and coupling, etc. to produce overlapping threshold voltage as appreciated by the present inventor. In particular, distributions 11, 21, and 31, represent idealized distributions of the threshold voltages associated with MLCs storing states 1, 2, and 3 respectively. (ST1-ST3).

Distributions 10, 20, and 30, represent increased distributions of threshold voltages for each of the states ST1-ST3 respectively when the MLCs store more states. As shown, an upper region of the distribution of threshold voltages associated with state ST1 overlaps with a lower region of the distribution 20 associated with state ST2. Further, an upper region of the threshold distribution 20 associated with state ST2 overlaps with a lower region of the distribution of threshold voltages associated with state ST3. In some embodiments according to the invention, a read voltage V_(rd1) is applied to the MLCs to discriminate between MLCs storing state ST1 and those storing ST2.

As appreciated by the present inventor, the read voltage V_(rd1) is located approximately at the intersection of the overlap in the respective distributions of threshold voltages 10 and 20 associated with the state ST1 and state ST2 respectively. Further, V_(rd1) is the read voltage which, likely, will activate a minimum number of MLCs when incrementing the read voltage from the lower threshold voltages associated only with state ST1 up to threshold voltages associated only with state ST2.

Still further, the read voltage V_(rd2) is used to access MLCs to discriminate between MLCs storing state ST2 and ST3. As shown, the read voltage V_(rd2) is located at an intersection of the threshold distributions 20 and 30, associated with states ST2 and ST3 respectively. As described above in reference to V_(rd1), the voltage V_(rd2) can be determined by accessing MLCs by incrementally increasing the read voltage starting with those associated only with state ST2 and proceeding upward to read voltages associated only with state ST3. Accordingly, the read voltage V_(rd2) is that voltage which will likely activate a minimum number of MLCs when incrementing the read voltage through the range described above.

Further, the read voltages V_(rd1) and V_(rd1) can be stored in the high voltage generator circuit 160 and applied to the selected rows of MLCs selected by the addressing during a read operation. Still further, these read voltages can be used to discriminate between states ST1, ST2, and SLT3 therefore, the register 161 can store a plurality of read voltages where each of the read voltages can be associated with discriminating between particular states.

FIG. 5 is a schematic representation of distributions of threshold voltages associated with states ST1 and ST2, and incremental preliminary read voltages applied by the read voltage adjustment circuit 140 to determine which preliminary read voltage activates a minimum number of MLCs between the two immediately adjacent states ST1 and ST2 in some embodiments according to the invention.

In particular, distributions 200 and 210 represent idealized distributions of threshold voltages associated with states ST1 and ST2 respectively. Further, distributions 205 and 215 represent wider distributions of threshold voltages also associated with states ST1 and ST2 respectively after the MLCs have been programmed. As shown in FIG. 5, a voltage V_(verify), is the verify voltage associated with state ST1, whereas the voltage V_(verify2) is the verification voltage associate with state ST2. It will be understood that, in some embodiments according to the invention. the application of a read voltage between V_(verify1) and V_(verify2) may only activate MLCs storing state 1. However, in some embodiments according to the invention where the distribution of threshold voltages for the MLCs are represented by distributions 205 and 215 for states ST1 and ST2 respectively, some of the MLCs storing state ST2 may be activated by a read voltage which is less than V_(verify2).

Accordingly, the read voltage adjustment circuit 140 applies a range of preliminary read voltages to the word lines associated with the MLCs between the upper read voltage limit (i.e., V₀ in FIG. 5) for the first state ST1 and a lower read voltage limit (i.e., V₁₀ in FIG. 5) for the second state ST2 (i.e., V_(verify2)). During the application of each of the incremental preliminary read voltages, the read voltage adjustment circuit 140 can monitor the number of MLCs activated in response to the preliminary read voltage.

Still referring to FIG. 5, the read voltage adjustment circuit 140 would begin the application of the range of preliminary read voltages starting with V₀ and determine the number of MLCs that are activated in response thereto. Subsequently, the read voltage adjustment circuit 140 repeatedly increments the preliminary read voltage to provide a read voltage in each of the regions 2-10 and, in turn, determines how many of the MLCs are activated in response to each of these separate preliminary read voltages. As shown in FIG. 5, in some embodiments according to the invention, a read voltage between V₄ and V₅ may activate a minimum number of MLCs. Accordingly, in such an embodiment, the read voltage adjustment circuit 140 may select a voltage between V₄ and V₅ for use as the read voltage in the register 161 included in the high voltage generator circuit 160 in response to a read operation.

FIG. 6 is a flowchart that illustrates operations of the read voltage adjustment circuit 140 in conjunction with the high voltage generator circuit 160 and MLC array 110 shown in FIG. 3 in some embodiments according to the invention. According to FIG. 6, operations begin with the read voltage adjustment circuit 140 applying an initial preliminary read voltage within the preliminary voltage range to the MLCs within the array 110 via the high voltage generator circuit 160 (Block 605).

It will be understood that the preliminary voltage range as well as the increment(s) used to increase the preliminary voltage for each of the determinations herein can be stored within the device 100, and may be provided during fabrication of the device. For example, in some embodiments according to the invention, the initial value (i.e., the upper read voltage limit for the first state shown in FIG. 5) as well as the lower read voltage limit for the second state ST2 shown in FIG. 5) are stored in the device 100. Furthermore, each of these voltages can be specified for each of the states that can be stored by the MLCs. In particular, the upper read voltage limit and the lower read voltage limit will be different for each pair of immediately adjacent states. For example, the next immediately greater states S3 and S4 will be associated with an upper read voltage limit for the second state as well as a lower read voltage limit for the fourth state.

The read voltage adjustment circuit 140 applies the preliminary read voltage to the MLCs which, in turn, may activate a number of the MLCs depending on the distribution of the threshold voltages associated with the particular state (Block 610). The read voltage adjustment circuit 140 then determines a number of MLCs that are activated in response to the application of the preliminary read voltage (Block 615).

If the read voltage adjustment circuit 140 determines that the current preliminary read voltage is not the last preliminary read voltage in the preliminary voltage range (Block 620), the read voltage adjustment circuit 140 increments the preliminary voltage to the next voltage within the preliminary voltage range (Block 625), whereupon operations continue with Block 610.

If, however, the read voltage adjustment circuit 140 determines that the current preliminary read voltage is the last preliminary read voltage in the preliminary read voltage range (Block 620), the read voltage adjustment circuit 140 determines which of the preliminary voltages activated the minimum number of MLCs within the preliminary voltage range (Block 630). For example, as shown in FIG. 5, the increment from V₄ to V₅ caused the minimum number of MLCs to be activated within the range. Therefore, in some embodiments according to the invention, the read voltage to be applied by the high voltage generator circuit 160 to discriminate between the two particular states separated by the preliminary voltage range tested above is identified as between V₄ and V₅. In some embodiments according to the invention, the read voltage can be determined within this range by taking the midpoint between V₄ and V₅. Other techniques may also be used.

After determining the read voltage to be used by the high voltage generator circuit 160 in response to read operations, the read voltage adjustment circuit 140 stores the selected read voltage in the register 161 included in the high voltage register circuit 160(Block 635).

FIG. 7 is a flowchart that illustrates operations of the read voltage adjustment circuit 140 used to determine the number of MLCs activated within a single increment of the preliminary voltage range in some embodiments according to the invention. In particular, the read voltage adjustment circuit 140 reads the MLCs using a first preliminary read voltage to provide first data from the MLCs (Block 705). The first preliminary read voltage is incremented (Block 710), to provide a second preliminary read within the preliminary voltage range.

The read voltage adjustment circuit 140 then reads the MLCs using the incremented preliminary read voltage (i.e., the second read voltage) to provide second data from the MLCs (Block 715). The read voltage adjustment circuit 140 then determines the number of bits from the MLCs to have toggled between the first and second data to provide a number of the MLCs activated between the first and second preliminary voltages discussed above in Blocks 710 and 715 respectively (Block 720). Accordingly, the operations outlined in FIG. 7 illustrate how the read voltage adjustment circuit 140 can determine the number of MLCs that are activated within a single interval within the preliminary voltage range as described above in reference to FIG. 6.

FIG. 8 is a flowchart that illustrates operations of the read voltage adjustment circuit 140 to determine the number of MLCs activated in a single increment of the preliminary voltage range in some embodiments according to the invention. According to FIG. 8, the read voltage adjustment circuit 140 reads the MLCs using a first preliminary read voltage to provide first data (Block 805) and the first preliminary read voltage is incremented to provide a second preliminary read voltage (Block 810). The read voltage adjustment circuit 140 then reads the MLCs using the second preliminary read voltage (Block 820).

The read voltage adjustment circuit 140 then determines the number of data bits activated between the first and second data to provide the number of MLCs activated between the first and second preliminary read voltages (Block 825). Accordingly, the operations outlined in FIG. 8 can be used, in some embodiments according to the invention, by the read voltage adjustment circuit 140 to determine the number of MLCs that are activated within a single increment of the preliminary voltage range as shown above in reference to FIG. 5.

The operations outlined in both FIGS. 7 and 8 can be used by the read voltage adjustment circuit 140 to determine the number of MLCs activated in each of the preliminary voltage ranges V₀-V₁₀ shown in FIG. 5. Furthermore, the read voltage adjustment circuit 140 can then compare the number of MLCs activated in each of these increments to determine overall which of the preliminary read voltages resulted in the minimum number of MLCs being activated in some embodiments according to the invention.

FIG. 9 is a schematic representation of distributions of threshold voltages associated with different states stored by MLCs according to separate logical pages in some embodiments according to the invention. In particular, the states shown in FIG. 9 can be logically organized as first through fourth pages where each of the pages represents a data bit stored by the MLCs. For example, the first through fourth pages shown in FIG. 9 can represent a total of sixteen states (i.e., four bits of storage) per MLC.

Furthermore, each of the bits stored within each page can be accessed separately from the other pages. For example, a read operation issued to the MLC array 110 shown in FIG. 3 can be executed as four separate accesses to the MLC where, for example, the first page (i.e., the LSB) is accessed first, followed by the second, third and fourth pages consecutively. Furthermore, each of the pages can be accessed using different read voltages that are determined as described above in reference to FIGS. 3-8. In particular, the read voltage between each of the immediately adjacent states shown in each of the pages can be determined by the read voltage adjustment circuit 140 so as to reduce the likelihood of errors being introduced when the MLC is used to store a relatively high density of data (i.e., sixteen states). Therefore, the high voltage generator circuit 140 and the register 161 therein can store each of the read voltages (V_(rd20)-V_(rd22) for the second page, V_(rd30)-V_(rd36) for the third page, and V_(rd40)-V_(rd414) for the fourth page).

FIG. 10 is a flowchart that illustrates operations of the read voltage adjustment circuit 140 to access data stored within the MLC and determine read voltages for each of the immediately adjacent states stored by the MLC in some embodiments according to the invention. According to FIG. 10, operations begin with the first page of the MLC (Block 1005). Program data is programmed to the current page within the MLC (Block 1010) and operations within the current page begin with a first state within the current page (Block 1015). Operations begin with a first preliminary read voltage within the preliminary read voltage range for the current state (Block 1020).

The read voltage adjustment circuit 140 determines the number of MLCs activated within the current preliminary voltage range (Block 1025). If the read voltage adjustment circuit 140 then determines that the current increment within the range is not the last increment (Block 1030), the current preliminary read voltage is incremented (Block 1035), to provide the next preliminary read voltage to be used by the read voltage adjustment circuit 140. If however, the read voltage adjustment circuit 140 determines that the current preliminary read voltage is the last increment within the range (Block 1030), the read voltage adjustment circuit 140 selects the read voltage to be used for the current preliminary voltage range (i.e., the read voltage to be used to discriminate between the immediately adjacent states (Block 1040). The read voltage is then stored in the register 160 in the high voltage generator circuit 160 (Block 1045).

If the read voltage adjustment circuit 140 determines that the current state within the page is not the last state within the page (Block 1050), the current state is incremented to provide the next state whereupon operations continue at Block 1020. If, however, the read voltage adjustment circuit 140 determines that the current state within the page is the last state (Block 1050), the read voltage adjustment circuit 140 then determines whether the current page is the last page within the MLC (Block 1060). If the current page is not the last page within the MLC (Block 1060), the read voltage adjustment circuit 140 increments the current page to provide the next page (Block 1065), whereupon operations continue with Block 1015. If, however, the read voltage adjustment circuit 140 determines that the current page is the last page within the MLC (Block 1060), operations may then end.

FIG. 11 is a schematic representation of a memory card 1100 including a non-volatile memory device 1110 in some embodiments according to the invention. According to FIG. 11, the non-volatile memory 1110 is coupled to a memory controller 1120 that includes a CPU 1122 that is configured to coordinate general operations of each of the components included in the memory controller 1120. The non-volatile memory 1110 includes the MLC array 110.

The memory controller 1120 also includes a host interface (I/F) 1123 that can be used to access a remote host, and an error checking and correction circuit (ECC) 1124 that can be used to protect data, for example, in an SRAM 1121 that the CPU 1122 can use to store data and commands used to operate the memory controller 1120. The memory controller 1120 also includes a memory interface 1125 that provides access to the non-volatile memory 1110, as described herein in some embodiments according to the invention.

FIG. 12 is a schematic representation of a memory system 1200 including the memory controller 1120 and the non-volatile memory 1110 as described in reference to FIG. 11. The memory system 1200 also includes a general operation processor 1230 that is used to coordinate operations of each of the subsystems included in the memory system 1200. The memory system 1200 also includes a random access memory (RAM) 1240 that can be used by the CPU 1230 to store data and commands used to operate the memory system 1200. The memory system 1200 also includes a user interface 1250 that may allow a user to direct operations of the memory system 1200.

Further, the memory system 1200 includes a power supply 1220 that can provide power for each of the subsystems included in the memory system 1200. It will be understood that the memory system 1200 can be embodied in any type of memory system, such as a memory card, a solid state disc, a camera image processor, an application chip set or the like. Further, the memory system 1200 (and the memory card 1100) can be mounted in various package types, such as a ball grid array, a chip scale package, a plastic leaded chip carrier, a plastic dual in-line package, a multi-chip package, a wafer level fabricated package, a wafer level processed stack package, or the like.

As described herein, embodiments according to the present invention can provide non-volatile memory devices including MLCs that are accessed using read voltages that are modified based on the application of incremental read voltages to determine a preferred voltage level used to discriminate between states stored by the MLC. For example, in some embodiments according to the invention, the MLC can be used to store 16 different states (i.e., four bits of data).

As appreciated by the present inventor, when the MLCs are used to store many states, the distribution of threshold voltages for the different states can increase compared to when relatively few states are stored in the MLC. Accordingly, the distributions of the threshold voltages associated with the different states (and particularly the states which are immediately adjacent to one another) can overlap one another so that an MLC that is used to store, for example, a fifth state can be activated in response to a threshold voltage which would otherwise fall within the nominal range of threshold voltages for the fourth state. If left unaddressed, this type of phenomenon can lead to an error during a read operation. Therefore, as appreciated by the present inventor, modifying the read voltages used to access the MLC may reduce the likelihood that an MLC storing an immediately adjacent state is erroneously activated.

Many alterations and modifications may be made by those having ordinary skill in the art, given the benefit of present disclosure, without departing from the spirit and scope of the invention. Therefore, it must be understood that the illustrated embodiments have been set forth only for the purposes of example, and that it should not be taken as limiting the invention as defined by the following claims. The following claims are, therefore, to be read to include not only the combination of elements which are literally set forth but all equivalent elements for performing substantially the same function in substantially the same way to obtain substantially the same result. The claims are thus to be understood to include what is specifically illustrated and described above, what is conceptually equivalent, and also what incorporates the essential idea of the invention. 

1. A method of operating a multi-level non-volatile memory device comprising: accessing data, stored in the device, that is associated with read voltages; and modifying the read voltages applied to a plurality of multi-level non-volatile memory cells to discriminate between states stored by the cells in response to a read operation to the multi-level non-volatile memory device.
 2. The method according to claim 1 wherein modifying comprises: modifying the read voltages applied to the plurality of multi-level non-volatile memory cells in response to subsequent read operations to the multi-level non-volatile memory device received after the read operation.
 3. The method according to claim 1 wherein modifying comprises: modifying the read voltages applied to the plurality of multi-level non-volatile memory cells in response to each read operation to the multi-level non-volatile memory device.
 4. The method according to claim 1 wherein modifying comprises: applying a range of preliminary read voltages to a word line, associated with the cells, between an upper read voltage limit for a first state and a lower read voltage limit for a second state that is immediately adjacent to the first state; determining which of the preliminary read voltages activated a minimum number of the plurality of multi-level non-volatile memory cells to provide a read voltage to discriminate between the first and second states; and applying the read voltage to the word line to read the plurality of multi-level non-volatile memory cells to execute the read command.
 5. The method according to claim 4 wherein determining further comprises: selecting the read voltage to be between two of the preliminary read voltages.
 6. The method according to claim 4 further comprising: storing the read voltage for subsequent use in accessing the cells.
 7. The method according to claim 4 wherein the read operation comprises a first read operation, the minimum number comprises a first minimum number, the read voltage comprises a first read voltage, the method further comprising: receiving a second read operation, subsequent to the first read operation, to read data from the plurality of multi-level non-volatile memory cells associated with the word line; applying the range of preliminary read voltages to the word line between the upper read voltage limit and the lower read voltage limit; determining which of the preliminary read voltages activated a second minimum number of the plurality of multi-level non-volatile memory cells to provide a second read voltage to discriminate between the first and second states; and applying the second read voltage to the word line to read the plurality of multi-level non-volatile memory cells to execute the second read operation.
 8. The method according to claim 4 wherein applying a range of preliminary read voltages to a word line further comprises: incrementing the preliminary read voltage starting from the upper read voltage limit to provide a first incremented preliminary read voltage; reading ones of the plurality of multi-level non-volatile memory cells having associated threshold voltages that are less than the incremented preliminary read voltage to provide first read data; incrementing the first preliminary read voltage to provide a second incremented preliminary read voltage; reading ones of the plurality of multi-level non-volatile memory cells having associated threshold voltages that are less than the second incremented preliminary read voltage to provide second read data; and detecting toggling of bits between the first and second data to determine a number of the plurality of the multi-level non-volatile memory cells that have associated threshold voltages between the first and second incremented preliminary read voltages.
 9. The method of claim 4 further comprising: repeatedly incrementing the preliminary read voltage until reaching the lower read voltage limit; reading the plurality of multi-level non-volatile memory cells for each of the preliminary read voltages provided by the repeatedly incrementing; and determining which reading of the cells, associated with the repeatedly incremented preliminary read voltages, activated a minimum number of the cells to provide the read voltage to discriminate between the first and second states.
 10. The method according to claim 4 wherein applying a range of preliminary read voltages to a word line further comprises: incrementing the preliminary read voltage starting from the upper read voltage limit to provide a first incremented preliminary read voltage; accessing the plurality of multi-level non-volatile memory cells using the first incremented preliminary read voltage; determining which of the plurality of multi-level non-volatile memory cells are not activated as having a threshold value greater than the first incremented preliminary read voltage to provide off multi-level non-volatile memory cells; incrementing the first preliminary read voltage to provide a second incremented preliminary read voltage; reading the off multi-level non-volatile memory cells by applying the second incremented preliminary read voltage to the word line; and determining a number of the off multi-level non-volatile memory cells that switch on in response to application of the second incremented preliminary read thereto to determine a number of the plurality of the multi-level non-volatile memory cells that have associated threshold voltages between the first and second incremented preliminary read voltages.
 11. A method of operating a multi-level non-volatile memory device comprising: receiving a read operation to read data from a plurality of multi-level non-volatile memory cells associated with a word line; applying a range of preliminary read voltages to the word line between an upper read voltage limit for a first state and a lower read voltage limit for a second state that is immediately adjacent to the first state; determining which of the preliminary read voltages activated a minimum number of the plurality of multi-level non-volatile memory cells to provide a read voltage to discriminate between the first and second states; and applying the read voltage to the word line to read the plurality of multi-level non-volatile memory cells to execute the read operation.
 12. The method according to claim 11 wherein determining further comprises: selecting the read voltage to be between two of the preliminary read voltages.
 13. The method according to claim 11 further comprising: storing the read voltage for subsequent use in accessing the cells.
 14. The method of claim 11 further comprising: repeatedly incrementing the preliminary read voltage until reaching the lower read voltage limit; reading the plurality of multi-level non-volatile memory cells for each of the preliminary read voltages provided by the repeatedly incrementing; and determining which reading of the cells, associated with the repeatedly incremented preliminary read voltages, activated a minimum number of the cells to provide the read voltage to discriminate between the first and second states.
 15. The method according to claim 11 wherein the read operation comprises a first read operation, the minimum number comprises a first minimum number, the read voltage comprises a first read voltage, the method further comprising: receiving a second read operation, subsequent to the first read operation, to read data from the plurality of multi-level non-volatile memory cells associated with the word line; applying the range of preliminary read voltages to the word line between the upper read voltage limit and the lower read voltage limit; determining which of the preliminary read voltages activated a second minimum number of the plurality of multi-level non-volatile memory cells to provide a second read voltage to discriminate between the first and second states; and applying the second read voltage to the word line to read the plurality of multi-level non-volatile memory cells to execute the second read operation.
 16. The method according to claim 11 wherein applying a range of preliminary read voltages to a word line further comprises: incrementing the preliminary read voltage starting from the upper read voltage limit to provide a first incremented preliminary read voltage; reading ones of the plurality of multi-level non-volatile memory cells having associated threshold voltages that are less than the incremented preliminary read voltage to provide first read data; incrementing the first preliminary read voltage to provide a second incremented preliminary read voltage; reading ones of the plurality of multi-level non-volatile memory cells having associated threshold voltages that are less than the second incremented preliminary read voltage to provide second read data; and detecting toggling of bits between the first and second data to determine a number of the plurality of the multi-level non-volatile memory cells that have associated threshold voltages between the first and second incremented preliminary read voltages.
 17. The method according to claim 11 wherein applying a range of preliminary read voltages to a word line further comprises: incrementing the preliminary read voltage starting from the upper read voltage limit to provide a first incremented preliminary read voltage; accessing the plurality of multi-level non-volatile memory cells using the first incremented preliminary read voltage; determining which of the plurality of multi-level non-volatile memory cells are not activated as having a threshold value greater than the first incremented preliminary read voltage to provide off multi-level non-volatile memory cells; incrementing the first preliminary read voltage to provide a second incremented preliminary read voltage; reading the off multi-level non-volatile memory cells by applying the second incremented preliminary read voltage to the word line; and determining a number of the off multi-level non-volatile memory cells that switch on in response to application of the second incremented preliminary read thereto to determine a number of the plurality of the multi-level non-volatile memory cells that have associated threshold voltages between the first and second incremented preliminary read voltages.
 18. A non-volatile memory device comprising: an array of multi-level non-volatile memory cells associated with respective word lines; a high voltage generator circuit configured to provide a read voltage to the array of multi-level non-volatile memory cells via the respective word lines during a read operation; a row decoder circuit configured to provide a row address to the array of multi-level non-volatile memory cells during the read operation; a column gating circuit configured to receive read data from cells in the array of multi-level non-volatile memory cells addressed by the row address during the read operation responsive to a column address; and a read voltage adjustment circuit configured to modify the read voltage applied to addressed ones of the cells to discriminate between states stored by the cells in response to the read operation to the non-volatile memory device.
 19. The non-volatile memory device according to claim 18 wherein the read voltage adjustment circuit is further configured to read data from the addressed cells using an addressed word line and configured to apply a range of preliminary read voltages to the word line between an upper read voltage limit for a first state and a lower read voltage limit for a second state that is immediately adjacent to the first state and configured to determine which of the preliminary read voltages activated a minimum number of the plurality of multi-level non-volatile memory cells to provide a read voltage to discriminate between the first and second states; and wherein the high voltage generator circuit is further configured to apply the read voltage to the addressed word line to read the plurality of multi-level non-volatile memory cells to execute the read operation.
 20. The non-volatile memory device according to claim 19 wherein the read voltage adjustment circuit is further configured to select the read voltage to be between two of the preliminary read voltages.
 21. The non-volatile memory device according to claim 19 wherein the high voltage generator circuit is further configured to store the read voltage for subsequent use in accessing the cells.
 22. An electronic system comprising: a processor configured to coordinate operations of an electronic system; a volatile memory, electrically coupled to the processor, configured to store and retrieve data responsive processor operations; a system interface, electrically coupled to the processor, configured to provide communications between the processor and external systems; and a non-volatile memory, electrically coupled to the processor, including at least one non-volatile memory device comprising: an array of multi-level non-volatile memory cells associated with respective word lines; a high voltage generator circuit configured to provide a read voltage to the array of multi-level non-volatile memory cells via the respective word lines during a read operation; a row decoder circuit configured to provide a row address to the array of multi-level non-volatile memory cells during the read operation; a column gating circuit configured to receive read data from cells in the array of multi-level non-volatile memory cells addressed by the row address during the read operation responsive to a column address; and a read voltage adjustment circuit configured to modify the read voltage applied to addressed ones of the cells to discriminate between states stored by the cells in response to the read operation to the non-volatile memory device.
 23. A memory card comprising: a non-volatile memory controller configured to coordinate operations of the memory card; and a non-volatile memory, electrically coupled to the non-volatile memory controller, comprising: an array of multi-level non-volatile memory cells associated with respective word lines; a high voltage generator circuit configured to provide a read voltage to the array of multi-level non-volatile memory cells via the respective word lines during a read operation; a row decoder circuit configured to provide a row address to the array of multi-level non-volatile memory cells during the read operation; a column gating circuit configured to receive read data from cells in the array of multi-level non-volatile memory cells addressed by the row address during the read operation responsive to a column address; and a read voltage adjustment circuit configured to modify the read voltage applied to addressed ones of the cells to discriminate between states stored by the cells in response to the read operation to the non-volatile memory device. 